GX3146 Datasheet, PDF (39/46 Pages) Semtech Corporation – Crosspoint Switch with Trace Equalization and Output De-emphasis

t5
SCLK
S_CS
SDIN
SDOUT
R/W
RSV
RSV Auto_Inc A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
R/W RSV
RSV Auto_Inc A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
t9
t6
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDIN signal is looped out on SDOUT
Read Data is output on SDOUT
Figure 4-12: Serial Host Interface Timing Diagram - Read Mode
Table 4-18: Serial Host Interface Timing
Parameter
Symbol
S_CS LOW before SCLK positive edge
t0
SCLK frequency
—
SCLK period
t1
SCLK duty cycle
t2
Input data setup time
t3
Time between end of Command Word
(or previous data word in
Auto-Increment mode) and the first
t4
SCLK of the following Data Word - write
cycle
Time between end of Command Word
(or previous data word in
Auto-Increment mode) and the first
t5
SCLK of the following Data Word - read
cycle
SDO hold time after SCLK negative edge
t6
S_CS HIGH after last SCLK negative edge
t7
Input data hold time
t8
S_CS HIGH time
t9
Conditions
50% levels;
3.3V or 1.8V
operation
Equiv.
Cycles
—
—
—
—
—
—
—
—
1.2
—
2.5
Min
7.0
0.1
40.0
40.0
7.0
40.0
70.0
5.0
9.0
5.0
18.5
Typ
Max Units
—
—
ns
—
25.0
MHz
—
10,000
ns
50.0
60.0
%
—
—
ns
—
—
ns
—
—
ns
—
16.0
ns
—
—
ns
—
—
ns
—
—
ns
70ns (t5) = 5 clock cycles at 135MHz plus SCLK and SDO signal propagation.
18.5ns (t9) = 2.5 clock cycles at 135MHz.
Max t6 (16ns) represents the latest time by which the SDO will be stable after the SCLK negative edge. As SDO
must be sampled on the SCLK positive edge, this determines the minimum SCLK period, and therefore the
maximum SCLK frequency.
SDO maximum transition time with 15pF load: 2ns.
SDO maximum transition time with 50pF load: 5ns.
Note 2: The GSPI and APPI are mutually exclusive (they can not both be used at the
same time).
GX3146 146 x 146 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-056075 March 2013
www.semtech.com
39 of 46
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