GX3146 Datasheet, PDF (33/46 Pages) Semtech Corporation – Crosspoint Switch with Trace Equalization and Output De-emphasis

4.11 Device Reset
The RESET pin is an active-LOW asynchronous reset for the device. Assertion of the
RESET pin sets the device in its minimum power state. The minimum pulse width of the
RESET signal is 10ms (t_reset). There is a 50μs delay (t_idle) between the RESET signal going
HIGH (inactive) and the device becoming operational. During this time (all of t_reset +
t_idle), there should be no host interface activity and the UPDATE_EN[7:0] pins must be
held LOW.
Note 1: RESET must be held LOW until all power supplies have stabilized.
Note 2: Upon emerging from reset, all SDI inputs and SDO outputs are powered-down,
pattern generation and checking is inactive, and all registers assume their reset values
as noted in the Semtech Crosspoint (GX3290 and family) Reference Manual (for CSRs).
RESET
t_reset
t_idle
Figure 4-6: Reset Timing Diagram
4.12 Host Interface
4.12.1 Parallel Host Interface Specifications
The Asynchronous Parallel Peripheral Interface (APPI) on the GX3146 device allows an
external host to access internal registers using parallel read and write operations.
The GX3146 APPI is selected by setting the HOST_S/P pin LOW.
Note: The S_CS pin must be pulled LOW when HOST_S/P is set LOW for parallel port
communication.
The host interface communicates with the Control and Status Registers (CSR) over an
APPI bridge. It is possible to write one register every 10ns (100MHz write update rate). It
is also possible to read one register every 20ns (50MHz read update rate).
The parallel interface is asynchronous. During writes, an active-LOW P_CS (Chip Select)
enables the interface and ADS (Address/Data Strobe) latches 12-bit write address and
16-bit write data into the device. During reads, the same P_CS signal is used, and the
ADS signal latches the 12-bit read address and then clocks out the 16-bit read data. The
P_R/W signal is used to differentiate between the two access types.
An auto-increment mode exists for both reads and writes. This mode is configured by
way of the APPI_AUTO_INCREMENT bit in the HOST_SETUP register. See Section 6 in
the Semtech Crosspoint (GX3290 and family) Reference Manual (for CSRs).
GX3146 146 x 146 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-056075 March 2013
www.semtech.com
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