GX3146 Datasheet, PDF (20/46 Pages) Semtech Corporation – Crosspoint Switch with Trace Equalization and Output De-emphasis

4. Detailed Description
4.1 Serial Data Input
Each of the GX3146 SDI inputs provide on-chip 100Ω differential terminations (or 50Ω
single-ended). Each is compatible with input differential amplitudes from 100mVppd to
1200mVppd, and input signal sources having CML outputs referred to DC supplies of
1.2V, 1.8V or 2.5V. Note that for AC-coupled inputs, the recommended supply voltage
for VCC_IN1 and VCC_IN2 is 1.8V.
Each of the 146 SDI input channels include frequency domain equalization,
independently-programmable to one of four levels, to compensate from 0 to 47 inches
(119 cm) of FR4 trace at 3Gb/s. The boost at the 1.5GHz Nyquist frequency, and
recommended trace length range, are shown under EQ_BOOST[287:0],
EXT_PG0_EQ_BOOST, EXT_PG1_EQ_BOOST in Table 4-1. See Figure 3-1.
Each input can be powered-down independently using the corresponding
EQ_POWERDOWN[287:0] or EXT_PG0_EQ_POWERDOWN or
EXT_PG1_EQ_POWERDOWN bit.
To accommodate input signal sources with 1.2V supplies and 1200mVppd signal
amplitudes, the input common mode point should be terminated to the respective
VCC_IN1 or VCC_IN2 supply.
The common mode termination connection to the respective VCC_IN1 or VCC_IN2
supply of each input can be independently controlled using the
EQ_TERMINATION[287:0] or EXT_PG0_EQ_TERMINATION or
EXT_PG1_EQ_TERMINATION bit (see Figure 3-1 and Table 4-1).
Note 1: When the HIZ_ACCM bit is set (register address 0x400h bit 0), inputs with their
common mode termination not connected to VCC_IN1 or VCC_IN2 are connected to an
internal common mode bias.
When an input EQ is powered-down, its common mode termination is automatically
disconnected from the corresponding VCC_IN1 or VCC_IN2.
For each of the inputs, there are control parameters (register address 0x401h to
0x522h). See Table 4-1 below.
Note 2: The EXT_PG01_SOURCE_PIN_PRBSB and EXT_PG1_SOURCE_PIN_PRBSB
bits in the TEST_SETUP register must be set to connect the EXT_PG0 and EXT_PG1 pins
to the matrix.
Table 4-1: Serial Data Input
EQ_BOOST[287:0], EXT_PG0_EQ_BOOST and
EXT_PG1_EQ_BOOST bits 1:0 (binary)
00
01
10
11
Boost Applied (@ nominal 1.5GHz)
0dB boost
3.5dB boost
7.6dB boost
12dB boost
0” to 6” (15 cm) trace
6” (15 cm) to 16”
(40 cm) trace
16” (40 cm) to 35”
(89 cm) trace
35” (89 cm) to 47”
(119 cm) trace
GX3146 146 x 146 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-056075 March 2013
www.semtech.com
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