GX3146 Datasheet, PDF (32/46 Pages) Semtech Corporation – Crosspoint Switch with Trace Equalization and Output De-emphasis

4.9 27MHz Reference Clock
The GX3146 requires an external 27MHz reference clock for correct operation. This
clock is multiplied to generate the digital core and interface clocks, and is also used to
synthesize video rate clocks in the pattern generation blocks, and to acquire video rate
signals in the pattern checker blocks. The reference clock has no impact on the jitter
measurement performance when the pattern checker blocks are locked to external data
sources, but has a direct impact on jitter performance within the loop bandwidth of the
CMU PLL in the pattern generation blocks.
The 27MHz reference clock can be generated by connecting a crystal between the
REF_CLK_IN and REF_CLK_OUT balls, along with appropriate loading capacitors and a
feedback resistor (see Figure 3-5). Alternatively, an LVCMOS 27MHz external clock
source can be connected to the REF_CLK_IN ball with the REF_CLK_OUT ball left
floating. The frequency variation of the crystal (including aging, supply and
temperature variation) should be less than +/-100ppm if the PRBS checking and
generation features are to be used in video applications.
4.10 Device Power-Up
Note 1: No power supply sequencing is required (see Section 4.11).
There is a 50μs delay (t_idle) between the power supplies reaching their nominal value
and the device becoming operational. During this time, there should be no host interface
activity, and the UPDATE_EN[7:0] pins must be held LOW.
The RC filter, shown in Figure 3-3, on each of the four VCO supplies—VCC_25_VCO0,
VCC_25_VCO1, VCC_25_VCO2 and VCC_VCO_DIGITAL—is required to minimize the
phase noise of the PLLs in pattern generation/detection modes, but the rise time of the
filter on VCC_VCO_DIGITAL in particular can impact the start-up time of the device
internal clock.
Note 2: In applications where power supplies reach their final voltage in under 1ms (the
time for the internal clock to start), approximately two time constants of the RC filter on
VCC_VCO_DIGITAL, can dominate the time for the GX3146 to emerge from reset upon
power-up. In such cases, the time for VCC_VCO_DIGITAL can be traded-off against
supply filtering and hence low-frequency jitter of patterns generated by Pattern
Generator Zero.
Note 3: RESET must be held LOW until all power supplies have stabilized.
{ ^{Nominal voltage}
Supply voltage ^{95% Nominal voltage}
t_idle
Figure 4-5: Power-Up Timing Diagram
GX3146 146 x 146 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-056075 March 2013
www.semtech.com
32 of 46
Proprietary & Confidential