GX3202 Datasheet, PDF (36/49 Pages) Semtech Corporation – Crosspoint Switch with Trace Equalization and Output De-emphasis

4.12 Host Interface
4.12.1 Parallel Host Interface Specifications
The Asynchronous Parallel Peripheral Interface (APPI) on the GX3202 device allows an
external host to access internal registers using parallel read and write operations.
The GX3202 APPI is selected by setting the HOST_S/P pin LOW.
NOTE: The S_CS pin must be pulled LOW when HOST_S/P is set LOW for parallel port
communication.
The host interface communicates with the Control and Status Registers (CSR) over an
APPI bridge. It is possible to write one register every 10ns (100MHz write update rate). It
is also possible to read one register every 20ns (50MHz read update rate).
The parallel interface is asynchronous. During writes, an active-LOW P_CS (Chip Select)
enables the interface and ADS (Address/Data Strobe) latches 12-bit write address and
16-bit write data into the device. During reads, the same P_CS signal is used, and the
ADS signal latches the 12-bit read address and then clocks out the 16-bit read data. The
P_R/W signal is used to differentiate between the two access types.
An auto-increment mode exists for both reads and writes. This mode is configured by
way of the APPI_AUTO_INCREMENT bit in the HOST_SETUP register. See Section 6 in
the Semtech Crosspoint (GX3290 and family) Reference Manual (for CSRs).
Table 4-12: APPI Inputs/Outputs
Signal Name
P_CS
P_ADS
P_R/W
P_ADD[11:0]
P_DAT[15:0]
I/O
Description
I
Chip Select from the host.
I
Address/Data Strobe from the host; used to “clock” address and
write data into the chip, and to “clock” read data out of the
chip.
I
Read/Write indication from the host; HIGH for read, LOW for
write.
I
Address from the host.
I/O Write data from the host, or read data to the host.
GX3202 202 x 202 3.5Gb/s Crosspoint
Data Sheet
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October 2012
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