GX3202 Datasheet, PDF (19/49 Pages) Semtech Corporation – Crosspoint Switch with Trace Equalization and Output De-emphasis

DIGITAL_CL_SEL
EXT_CLK_DIGITAL
EXT_CLK_DIGITAL
REF_CLK_IN
REF_CLK_OUT
/2
XTAL
OSC.
CMU
0
Pattern
TX0
1
NOTE: The clock used to drive Pattern Generator TX0 is also used to derive the clock timing for the digital core. Therefore, GSPI/APPI interface timing and
update timing will track the external clock frequency if one is selected from the EXT_CLK_DIGITAL/EXT_CLK_DIGITAL pins for Pattern Generator TX0.
BIST_RX_5 0x83C b4
EXT_CLK0
EXT_CLK0
REF_CLK_IN
REF_CLK_OUT
/2
XTAL
OSC.
CMU
0
Pattern
RX0
1
EXT_CLK1
EXT_CLK1
REF_CLK_IN
REF_CLK_OUT
BIST_RX_5 0x83C b6
/2
XTAL
OSC.
CMU
0
Pattern
RX1
1
EXT_CLK2
EXT_CLK2
REF_CLK_IN
REF_CLK_OUT
BIST_TX_0 0x823 b0
/2
XTAL
OSC.
CMU
0
Pattern
TX1
1
Figure 3-4: PRBS Generator/Checker Clock Selection
REF_CLK_IN
REF_CLK_OUT
Using a crystal
1MΩ
C1
27MHz
C2
Using a single-ended 27MHz oscillator
REF_CLK_IN
27MHz Oscillator
REF_CLK_OUT
NOTE: The value of the C1 and C2 load capacitors are
dependent on the chosen crystal.
Figure 3-5: Crystal Oscillator
GX3202 202 x 202 3.5Gb/s Crosspoint
Data Sheet
56077 - 1
October 2012
19 of 49
Proprietary & Confidential