GX3202 Datasheet, PDF (28/49 Pages) Semtech Corporation – Crosspoint Switch with Trace Equalization and Output De-emphasis

The CDR integrated in each Rx block can independently lock to data at rates of 270Mb/s,
1.485Gb/s and 2.97Gb/s. Other rates up to 3Gb/s can be analyzed by providing an
external clock signal of 2x, 4x, or 22x the desired bit rate, with a maximum external
clock frequency of 6GHz. Note that retiming is not possible when using an external
clock signal for the Rx block. The external clock must be synchronous with any data to
be checked and the RX0_PRBS_CHK_MODE bits must be set to a value of '01'. The two
pattern checker “Rx” blocks in the GX3202 can each independently check PRBS 2⁷-1,
PRBS 2¹⁵-1, and PRBS 2²³-1 data patterns.
Table 4-6: Rx External Clocks
RX0
EXT_CLK0 (R35)
EXT_CLK0 (T35)
RX1
EXT_CLK1 (AJ15)
EXT_CLK1 (AH15)
The error checking modes are selected by the RX0_PRBS_CHK_MODE bits and the
RX1_PRBS_CHK_MODE bits (addresses 0x804h and 0x810h respectively).
Table 4-7: Checking Modes
RX0_PRBS_CHK_MODE[1:0] (binary)
00
01
10 or 11
Input Mode
Check data sampled at neutral phase
Check data sampled at adjustable phase
Compare nominally sampled data with phase
offset data (allows eye monitoring of
arbitrary patterns)
The pattern checker will check for the PRBS pattern specified by the
RX0_PRBS_POLYNOMIAL and RX1_PRBS_POLYNOMIAL bits (addresses 0x803h
and 0x811h respectively).
The PRBS checkers are enabled by the RX0_PRBS_ENABLE and RX1_PRBS_ENABLE
bits (register address 0x81Dh[1:0]).
Table 4-8: Checked Patterns
RX0_PRBS_POLYNOMIAL[1:0] (binary)
00
01
10
Pattern Checked
PRBS7
PRBS15
PRBS23
GX3202 202 x 202 3.5Gb/s Crosspoint
Data Sheet
56077 - 1
October 2012
28 of 49
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