GX3202 Datasheet, PDF (25/49 Pages) Semtech Corporation – Crosspoint Switch with Trace Equalization and Output De-emphasis

and 0x321h, respectively. Also, the MON0 and MON1 outputs are terminated to the
VCC_25_A supply.
4.4 Propagation Delay
The propagation delay is dependent on the path that the signal takes through the device.
Although the delay difference from the shortest path to the longest path could be up to
5.5ns, this difference is at a minimum for connections from inputs numerically close
together and on the same side of the device to outputs that are numerically close
together and on the same side of the device. Propagation delay differences of less than
750ps can be expected when the inputs are adjacent in the ballout and the outputs are
also adjacent in the ballout.
4.5 Using Multiple Strobes
The GX3202 has eight fully-independent update strobes.
Outputs 287 to 0 can be assigned to one of the eight strobes through the setting of the
UPDATE_SELECT bits in the corresponding DYNAMIC[287:0] register. The input
signal selection, output power switching and signal inversion will take effect on the
LOW-to-HIGH edge of its assigned strobe signal or bit. This allows different portions of
the crosspoint to be switched at different points in time. This is particularly useful in
systems supporting multiple data or video formats, where the switch point/time varies
from format to format.
4.6 Pattern Generator and Pattern Checker
4.6.1 Pattern Generator
NOTE 1: There are two pattern generator “Tx” blocks in the GX3202. In the following,
wherever only TX0 is mentioned, the corresponding is also true for TX1.
NOTE 2: When the PRBS Generator is disabled, the generated signal does not
completely terminate. The PRBS polynomial bits must be re-written in order to
terminate the signal.
The two pattern generator “Tx” blocks in the GX3202 can each independently generate
PRBS 2⁷-1, PRBS 2¹⁵-1, and PRBS 2²³-1 data patterns, or alternating 1's and 0's. The
built-in clock multiplier PLLs independently synthesize rates of 270Mb/s and 2.97Gb/s
from the required, external 27MHz reference clock (see Section 4.9). Other rates up to
3Gb/s can be generated by providing an external clock signal at 2x, 4x, or 22x the
desired bit rate to TX1, with a maximum external clock frequency of 6GHz.
Table 4-4: Tx External Clocks
TX0
EXT_CLK_DIGITAL (AJ35)
EXT_CLK_DIGITAL (AH35)
TX1
EXT_CLK2 (R15)
EXT_CLK2 (T15)
GX3202 202 x 202 3.5Gb/s Crosspoint
Data Sheet
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October 2012
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