SKYPER42R Datasheet, PDF (13/18 Pages) Semikron International – IGBT Driver Core

SKYPER^® 42 R
4.2. Under Voltage Protection of driver power supply (UVP)
The internally detected supply voltage of the driver has an under voltage protection.
Supply voltage
Regulated +15V ±4%
UVP level
Typ 13,5V
If the internally detected supply voltage of the driver falls below this level, the IGBTs will be switched off (IGBT
driving signals set to LOW). The input side switching signals of the driver will be ignored. The error memory will
be set, and the output PRIM_nERROR_OUT changes to the HIGH state.
4.3. Short Pulse Suppression (SPS)
This circuit suppresses short turn-on and off-pulses of incoming signals. This way the IGBTs are protected
against spurious noise as they can occur due to bursts on the signal lines. Pulses shorter than 625ns are
suppressed and all pulses longer than 750ns get through for 100% probability. Pulses with a length in-between
625ns and 750ns can be either suppressed or get through.
Pulse pattern – SPS
short pulses
PRIM_TOP/BOT_IN (HIGH)
PRIM_TOP/BOT_IN (LOW)
SEC_TOP/BOT_IGBT_ON
SEC_TOP/BOT_IGBT_OFF
4.4. Dead Time generation (Interlock TOP / BOT) (DT)
The DT circuit prevents, that TOP and BOT IGBT of one half bridge are switched on at the same time (shoot
through). The dead time is not added to a dead time given by the controller. Thus the total dead time is the
maximum of "built in dead time" and "controller dead time". It is possible to control the driver with one switching
signal and its inverted signal.
Please note:
The generated dead time is fixed at 2 µs and cannot be changed. Please contact your resonsible sales engineer for customization.
Pulse pattern – DT
The total propagation delay of the driver is the sum of
interlock dead time (tTD) and driver input output signal
propagation delay (td(on;off)IO) as shown in the pulse pattern.
Moreover the switching time of the IGBT chip has to be taken
into account (not shown in the pulse pattern).
In case both channel inputs (PRIM_TOP_IN and
PRIM_BOT_IN) are at high level, the IGBTs will be turned off.
If only one channel is switching, there will be no interlock
dead time.
Please note:
No error message will be generated when overlap of switching signals occurs.
12
2011-04-04 – Rev05
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