LC87F83C8A Datasheet, PDF (3/31 Pages) Sanyo Semicon Device – FROM 128K byte, RAM 6K byte on-chip 8-bit ETR Microcontroller

LC87F83C8A/C8AU/96A/96AU/64A/64AU
■SIO: 3 channels
• SIO 0: 8 bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (4/3 to 512/3 tCYC transfer clock cycle)
3) Automatic continuous data transmission (1 to 256 bits)
• SIO 1: 8 bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2 to or 3 to wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (Half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
• SIO2: 8 bit synchronous serial interface
1) LSB first mode
2) Built-in 3-bit baudrate generator (4/3 to 512/3 tCYC transfer clock cycle)
3) Automatic continuous data transmission (1 to 32 bytes)
■UART: 2 channels
1) Full duplex
2) 7/8/9 bit data bits selectable
3) 1 stop bit (2 bits in continuous transmission mode)
4) Built-in 8-bit baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
■AD Converter: 8 bits × 10 channels
■PWM: Multifrequency 12-bit PWM × 4 channels
■Remote Control Receiver Noise Filtering Function (sharing pins with P73, INT3, and T0IN)
1) Noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
■Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
■Interrupts
• 29 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/Base timer (BT0, 1)
5
00023H
H or L
T0H/INT6
6
0002BH
H or L
T1L/T1H/INT7
7
00033H
H or L
SIO0/UART1 receive/UART2 receive
8
0003BH
H or L
SIO1/SIO2/UART1 transmit/UART2 transmit
9
00043H
H or L
ADC/T6/T7/PWM4, PWM5
10
0004BH
H or L
Port 0/T4/T5/PWM0, PWM1
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• The Base timers are two interrupt sources of BT0 and BT1, it is one interrupt source by PWM0 and 1, it is one
interrupt source by PWM4 and 5.
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