LC87F83C8A Datasheet, PDF (12/31 Pages) Sanyo Semicon Device – FROM 128K byte, RAM 6K byte on-chip 8-bit ETR Microcontroller

LC87F83C8A/C8AU/96A/96AU/64A/64AU
3. SIO2 Serial I/O Characteristics (Note 4-3-1)
Parameter
Symbol
Pins/
Remarks
Conditions
Frequency
Low level
pulse width
High level
pulse width
Frequency
Low level
pulse width
High level
pulse width
Data setup time
Data hold time
tSCK(5)
tSCKL(5)
tSCKH(5)
tSCKHA(5a)
tSCKHA(5b)
tSCK(6)
tSCKL(6)
tSCKH(6)
tSCKHA(6a)
tSCKHA(6b)
tsDI(3)
thDI(3)
SCK2
(SI2P2)
• See Fig. 2.
SCK2
(SI2P2)
SCK2O
(SI2P3)
• Continuous data
transmission/reception mode of
SIO0 is not in use simultaneous.
• See Fig. 2.
• (Note 4-3-2)
• Continuous data
transmission/reception mode of
SIO0 is in use simultaneous.
• See Fig. 2.
• (Note 4-3-2)
• CMOS output selected.
• See Fig. 2.
SI2(SI2P1),
SB2(SI2P1)
• Continuous data
transmission/reception mode of
SIO0 is not in use simultaneous.
• CMOS output selected.
• See Fig. 2.
• Continuous data
transmission/reception mode of
SIO0 is in use simultaneous.
• CMOS output selected.
• See Fig. 2.
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 2.
VDD[V]
min
2
1
1
3.0 to 5.5
4
7
4/3
3.0 to 5.5 tSCKH(6)
+(5/3)tCYC
tSCKH(6)
+(5/3)tCYC
0.03
3.0 to 5.5
0.03
Specification
typ
max
unit
tCYC
1/2
tSCK
1/2
tSCKH(6)
+(10/3)tCYC
tCYC
tSCKH(6)
+(19/3)tCYC
Output delay
tdD0(5)
SO2(SI2P0), • Must be specified with respect to
μs
time
SB2(SI2P1) falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
change in open drain output
3.0 to 5.5
(1/3)tCYC
+0.05
mode.
• See Fig. 2.
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input, a time from SI2RUN being set when serial clock is "H" to the first negative edge
of the serial clock must be longer than tSCKHA.
No.A1780-12/31