LC87F83C8A Datasheet, PDF (27/31 Pages) Sanyo Semicon Device – FROM 128K byte, RAM 6K byte on-chip 8-bit ETR Microcontroller

LC87F83C8A/C8AU/96A/96AU/64A/64AU
VREG, AVSS Terminal condition
It is necessary to place capacitors between VREG and AVSS as describe below.
• Place capacitors as close to VREG and AVSS as possible.
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L4 = L4’).
• Capacitance of C4 must be more than 1μF to 10μF.
• Use thicker pattern for VREG and AVSS.
L4
AVSS
C4
VREG
L4’
VDDx, VSSx Terminal condition x=2, 4
• It is necessary to place capacitors between VDDx and VSSx as describe below.
• Place capacitors as close to VDDx and VSSx as possible.
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L5 = L5’).
• Capacitance of C5 must be more than 0.1μF.
• Use thicker pattern for VDDx and VSSx.
L5
VSSx
C5
VDDx
L5’
VDD
RRES
(Note) Select CRES and RRES value to assure that reset is
generated after the VDD becomes higher than the
minimum operating voltage.
RES
Recommended value
CRES
CRES: 0.47μF
RRES: 270kΩ
Figure 1 Reset Circuit
No.A1780-27/31