LV4147W Datasheet, PDF(22/26 Page) Sanyo Semicon Device – Bi-CMOS LSI For LCD Panel Drive Single Chip IC

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LV4147W Datasheet, PDF (22/26 Pages) Sanyo Semicon Device – Bi-CMOS LSI For LCD Panel Drive Single Chip IC

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LV4147W

(4) Data specifications 1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Description

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not used

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Not used

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRAP ON

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 TRAP OFF

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not used

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Not used

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 System changeover NTSC

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 System changeover PAL

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 External VSYNC input OFF

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 External VSYNC input ON

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Y/color difference clamp position, pedestal

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Y/color difference clamp position, SYNC

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sample hold phase SHS1

(Note 1)

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Sample hold phase SHS2

(Note 1)

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Sample hold phase SHS3

(Note 1)

0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Sample hold phase ALL through

(Note 1)

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 HD output polarity, positive

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 HD output polarity, negative

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 VD output polarity, positive

0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 VD output polarity, negative

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Panel selection 521 Ã 218 : 110,000 mode

0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 Panel selection 557 Ã 234 : 130,000 mode

0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 Panel selection 800 Ã 225: 180,000 mode

0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 For test. Do not set this bit to "1".

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Field overlap method, odd number on even number

0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 Field overlap method, even number on odd number

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Normal mode

(Note 6)

0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 521Ã218 (EVF) + 557Ã234 (monitor) driving (Note 6-3)

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 BLHD output ON

0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 BLHD output Stop

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Sync generator function, OFF

0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 Sync generator functionON (output other than HD, VD, BLHD, and SPCLK is turned OFF).

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Normal mode

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 For test. Do not set this bit to "1".

0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 For test. Do not set this bit to "1".

0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 For test. Do not set this bit to "1".

0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 Skipping OFF mode for PAL (Indication of no skipping)

0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 For test. Do not set this bit to "1".

0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 Not used

0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 Not used

0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 Not used

0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Normal mode

0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 For test. Do not set this bit to "1".

0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 For test. Do not set this bit to "1".

0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 For test. Do not set this bit to "1".

0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 For test. Do not set this bit to "1".

0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 Not used

0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 For test. Do not set this bit to "1".

0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 For test. Do not set this bit to "1".

0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 For test. Do not set this bit to "1".

Default

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