LV4147W Datasheet, PDF (21/26 Pages) Sanyo Semicon Device – Bi-CMOS LSI For LCD Panel Drive Single Chip IC

(2) 3-wave serial format
LV4147W
DATA
SCLK
LOAD
Data length : 16bit
Clock frequency : 3MHz or less
Only when SCLK is input in 16-bit clock while LOAD is in the L period, DATA is accepted at rise of
LOAD.
Note : When SCLK is in 15-bit or 17-bit clock while LOAD is in the L period, DATA is not accepted.
(3) Data output timing
1. Various mode settings
DATA accepted at rise of LOAD is set at fall of the vertical sync signal.
When the data is transmitted several times for the same item, the data immediately before the vertical sync signal
becomes valid.
2. Setting of the electric volume
Concurrently with acceptance of DATA at rise of LOAD, the D/A output data is changed.
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