LC87F2708A Datasheet, PDF (20/21 Pages) Sanyo Semicon Device – CMOS IC FROM 8K byte, RAM 512 byte on-chip 8-bit 1-chip Microcontroller

VDD
Reset unknown-state
(POUKS)
RES
LC87F2708A
(a)
(b)
POR release voltage
(PORRL)
Reset period
100μs or longer
Reset period
Figure 6 Example of POR Only (LVD Deselected) Mode Waveforms
(at Reset Pin with RRES Pull-up Resistor Only)
• The POR circuit generates a reset signal only when the power voltage is raised from the VSS level.
• No stable reset signal is generated if power is turned on again when the power voltage does not go down to the VSS
level as shown in (a). If this case is anticipated, use the LVD function as explained below or configure an external
reset circuit.
• A reset is effected only when power is turned on again after the power voltage goes down to and remains at the VSS
level for 100μs or longer as shown in (b).
LVD hysteresis width
(LVHYS)
LVD release voltage
(LVDET+LVHYS)
VDD
Reset unknown-state
(LVUKS)
RES
Reset period
Reset period
Reset period
LVD voltage
(LVDET)
Figure 7 Example of POR + LVD Mode Waveforms
(at Reset Pin with RRESS Pull-up Resistor Only)
• A reset is effected both when power is turned on and when it goes down.
• The hysteresis width (LVHYS) is introduced in the LVD circuit to prevent the iterations of the IC entering and exiting
the reset state near the detection threshold level.
No.A1335-20/21