LC87F2708A Datasheet, PDF (13/21 Pages) Sanyo Semicon Device – CMOS IC FROM 8K byte, RAM 512 byte on-chip 8-bit 1-chip Microcontroller

LC87F2708A
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = 0V
Parameter
Symbol
Pin/Remarks
Conditions
Specification
VDD[V]
min.
typ. max.
unit
High/low level tPIH(1) INTA(P30),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INTB(P31),
• Event inputs for timers 0 and 1 are
INTD(P33),
INTE
enabled.
2.7 to 5.5
1
(P10, P11, P14, P15),
INTF(P12, P13, P16)
tPIH(2) INTC(P32) when noise • Interrupt source flag can be set.
tPIL(2)
filter time constant is
• Event inputs for timer 0 are
2.7 to 5.5
1
"none"
enabled.
tPIH(3) INTC(P32) when noise • Interrupt source flag can be set.
tPIL(3)
filter time constant is
• Event inputs for timer 0 are
2.7 to 5.5
64
"1/16"
enabled.
tCYC
tPIH(4)
tPIL(4)
INTC(P32) when noise
filter time constant is
"1/32"
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
2.7 to 5.5
128
tPIH(5)
tPIL(5)
INTC(P32) when noise
filter time constant is
"1/64"
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
2.7 to 5.5
256
tPIH(6)
tPIL(6)
HCT1IN(P30)
Pulses can be recognized as signals
by the high-speed pulse width/period 2.7 to 5.5
3
counter 1.
H1CK
(Note 5-1)
tPIH(7) HCT2IN(P11, P31)
Pulses can be recognized as signals
tPIL(7)
by the high-speed pulse width/period 2.7 to 5.5
6
counter 2.
H2CK
(Note 5-2)
tPIL(8)
RES
Resetting is enabled.
2.7 to 5.5
200
μs
Note 5-1: H1CK denotes the period of the base clock (1 to 8 × high-speed RC oscillation clock or system clock) for the
high-speed pulse width/period counter 1.
Note 5-2: H2CK denotes the period of the base clock (2 to 16 × high-speed RC oscillation clock or system clock) for
the high-speed pulse width/period counter 2.
Comparator Characteristics at Ta=-40°C to +85°C, VSS1 = 0V
Parameter
Symbol
Pin/Remarks
Conditions
Common mode
input voltage
range
Offset voltage
VCMIN
VOFF
IN0+(P11),
IN0-(P12),
IN1+(P15),
IN1-(P16)
Within common mode input voltage range
Response time tRT
• Within common mode input voltage
range
• Input amplitude=100mV
• Overdrive=50mV
Operation
stabilization
tCMW
time
(Note 6-1)
Note 6-1: The interval after CMPON is set till the operation gets stabilized.
VDD[V]
2.7 to 5.5
2.7 to 5.5
2.7 to 5.5
2.7 to 5.5
Specification
min
typ
max unit
VSS
VDD
V
-1.5
±10
±30 mV
200
600
ns
1.0 μs
No.A1335-13/21