LC8904Q Datasheet, PDF (17/20 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC8904Q
Analog Source Mode
The LC8904Q enters analog source mode in the following two cases:
1. Analog source mode is selected from the microprocessor interface.
2. If the input pin specified for data demodulation goes to the no signal state.
In this mode, the clock that operates the whole system is taken from the crystal oscillator clock, and the PLL and data
demodulation circuits are stopped. The BCLK, LRCK, CLKOUT1, and CLKOUT2 clocks are output.
The output pins have the following functions in analog source mode:
1. DOUT/V
Data output as specified by the microprocessor interface
2. ERROR
Outputs the error state, i.e. a high level.
3. SUB1 and SUB2
These pins output the “#1” lock error state.
4. DATAOUT
Outputs the lock error state, i.e., a low level.
5. EMPHA
Outputs the lock error state, i.e., a low level.
6. Microprocessor interface codes
Input codes: The codes loaded from the microprocessor interface are retained.
Output codes: The same codes as output for a PLL lock error.
Crystal Oscillator
1. A built-in detector circuit determines whether or not a data input signal is present. This circuit operates from either
the VCO or the crystal oscillator clock. When the power supply is coming up, this clock is supplied from the VCO,
and if a no-data state is detected, the system switches to the crystal oscillator clock. Here, if the clock is not supplied
from the crystal oscillator after a no-data state is detected, the whole system goes to the stopped state, and, since the
detector circuit does not operate even if data is supplied, the system will remain in the stopped state.
2. The XIN and XOUT pins include a built-in oscillator amplifier circuit, and operate as follows when a crystal
oscillator element is attached.
Pin
Data present*
No data
XIN
H
Crystal oscillator input accepted
XOUT
L
Outputs the inverse of the XIN pin state.
Note: * When data is present, the XIN pin is pulled up internally.
Data Output Timing
1. Data is output in synchronization with the falling edge of the BCLK signal.
2. Data, BCLK, and LRCK are output in synchronization with the rising edge of the 256fs clock.
3. The figure on the following page shows the data output timing.
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