LC8904Q Datasheet, PDF (10/20 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC8904Q
The LC8904Q subcode interface uses the user bit subcode sync word and start bit for system timing extraction.
Therefore, since SBSY and SFSY will change with that timing, user bit transmission must follow the table shown below
when using the values of t_BW, t_F, t_CHW, t_CLW, and t_CD with the specifications listed in the preceding tables.
Note: 1. The subcode sync word is defined as the block sync section (block start) when 0-valued data has been received consecutively for at least 22 bits.
2. The period of the frame sync signal S0 is 90.7 µs. The S1 period also has a minimum length of 90.7 µs (when 0-valued data is received
consecutively for 22 bits), depending on the subcode sync word period. Not that the shortest word is 10 bits.
3. The SBCK signal input delay (t_HD) and pulse widths (t_CHW and t_CLW) must be set to values less than or equal to the typical values when the
shortest user data word length is used.
No. 5014-10/20