LC8904Q Datasheet, PDF (13/20 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC8904Q
The microprocessor interface controls the following settings and outputs.
1. System stop
2. Data input pin settings
3. Validity flag (V flag) output selection
4. Analog source mode setting
5. Output data format setting
6. Channel status (32 bits) output
7. Output of the 80-bit subcode Q data with CRC flags.
• CCB/SUB pin
The CCB/SUB pin selects one of two formats. The clocks and codes must be set up appropriately for each of these
formats. SRDT is the output pin when CCB/SUB is low. SRDT goes to the high-impedance state when the
CCB/SUB pin is high, during writes, and when an address for a different output is latched. In contrast with the
SRT pin, the DO pin is a high-level open drain output that functions as the output pin when CCB/SUB is high.
• Data I/O address
Address are allocated according to the differing formats as listed below.
Format
CCB/SUB = low
CCB/SUB = high
I/O
B0 B1 B2 B3 A0 A1 A2 A3
B0 B1 B2 B3 A0 A1 A2 A3
Data input
EA 0 1 0 1 0 1 1 1 F7 1 1 1 0 1 1 1 1
Data output (C bits)
E9 1 0 0 1 0 1 1 1 F8 0 0 0 1 1 1 1 1
Data output (subcode Q)
E8 0 0 0 1 0 1 1 1 F9 1 0 0 1 1 1 1 1
• Input
The DIN1 to DIN4 data input pins have built-in amplifiers, and can accept signals with amplitudes of about
400 Vp-p. Note that the DOUT pin can be set up to output the EIAJ format data by microprocessor interface
commands. (It can also be used to output the V flag.)
• Input code settings
System stop by stopping both the VCO and crystal oscillators (DI4)
DI4
L
System
Run
H
Stop
Selection of data to demodulate (DI5, DI6)
DI5
DI6
Demodulation data input
L
L
DIN1
H
L
DIN2
L
H
DIN3
H
H
DIN4
Input data (EIAJ format) output selection
DI7
DI8
DOUT/V pin
L
L
DIN1
H
L
DIN2
L
H
DIN3
H
H
DIN4
No. 5014-13/20