LC8904Q Datasheet, PDF (15/20 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC8904Q
— When the 96 bits of the subcode Q data have been read in with the PLL circuit in the locked state, a sync signal
that has a low period with a pulse width of 136 µs is output by outputting at least 22 bits of continuous 0-valued
data after the 96 bits of W data (W97) from DQSY. Note that this sync signal low-level pulse will not be output
unless 96 bits of subcode Q data including the CRC flags are input.
When not Using the Microprocessor Interface
If the LC8904Q is used without using the microprocessor interface, the microprocessor interface pins must be tied to
fixed levels and data only input to pin DIN1. This configuration can be useful as a simplified circuit evaluation method.
CD Subcode Interface
The LC8904Q outputs CD subcode data from the SFSY, SBCK, PW, and SBSY pins. These pins output user bits that
were transmitted according to the CP-1201 standard and that were converted to the CP-2401 standard.
The timing of the rise and fall of the SFSY signal is converted into that shown in the figure below according to the
timing of the start bit in the user bits in the input data.
No. 5014-15/20