K4H510438D Datasheet, PDF (9/24 Pages) Samsung semiconductor – 512Mb D-die DDR SDRAM Specification

K4H510438D
K4H510838D
K4H511638D
DDR SDRAM
8.0 Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
COMMAND
CKEn-1 CKEn CS
RAS CAS
WE BA0,1 A10/AP
A0 ~ A9,
A11 ~ A12
Note
Register
Extended MRS
H
X
L
L
L
L
OP CODE
1, 2
Register
Mode Register Set
H
X
L
L
L
L
OP CODE
1, 2
Auto Refresh
H
3
H
L
L
L
H
X
Entry
L
3
Refresh
Self
Refresh
LH
H
H
Exit
L
H
X
3
HX
X
X
3
Bank Active & Row Addr.
H
X
L
L
H
H
V
Row Address
Read &
Auto Precharge Disable
L
Column Address _{Auto Precharge Enable}
H
X
L
H
L
H
V
H
Column
4
Address
4
Write &
Auto Precharge Disable
L
Column Address _{Auto Precharge Enable}
H
X
LH
L
L
V
H
Column
Address
4
4, 6
Burst Stop
H
X
LH
H
L
X
7
Precharge
Bank Selection
All Banks
V
L
H
X
L
L
H
L
X
H
X
5
HX
X
X
Entry
H
L
Active Power Down
L
V
V
V
X
Exit
L
HXX
X
X
HX
X
X
Entry
H
L
LH
H
H
Precharge Power Down Mode
X
HX
X
X
Exit
L
H
L
V
V
V
DM(UDM/LDM for x16 only)
H
X
X
8
HX
X
X
9
No operation (NOP) : Not defined
H
X
X
LH
H
H
9
Note :
1. OP Code : Operand Code. A0 ~ A12& BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges
(Write UDM/LDM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.2 January 2006