K4H510438D Datasheet, PDF (16/24 Pages) Samsung semiconductor – 512Mb D-die DDR SDRAM Specification

K4H510438D
K4H510838D
K4H511638D
DDR SDRAM
19.0 AC Timming Parameters & Specifications
Parameter
CC
B3
A2
B0
Symbol ^{(DDR400@CL=3.0) (DDR333@CL=2.5) (DDR266@CL=2.0) (DDR266@CL=2.5)} Unit Note
Min Max Min Max Min Max Min Max
Row cycle time
tRC
55
60
65
65
ns
Refresh row cycle time
tRFC
70
72
75
75
ns
Row active time
tRAS
40
70K
42
70K
45
70K
45
70K ns
RAS to CAS delay
tRCD
15
18
20
20
ns
Row precharge time
tRP
15
18
20
20
ns
Row active to Row active delay
tRRD
10
12
15
15
ns
Write recovery time
tWR
15
15
15
15
ns
Last data in to Read command
tWTR
2
1
1
1
tCK
CL=2.0
-
-
7.5
12
7.5
12
10
12
ns
Clock cycle time
CL=2.5 tCK
6
12
6
12
7.5
12
7.5
12
ns
CL=3.0
5
10
-
-
-
-
-
-
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55 tCK
Clock low level width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
DQS-out access time from CK/CK
tDQSCK -0.55 +0.55 -0.6
+0.6 -0.75 +0.75 -0.75 +0.75 ns
Output data access time from CK/CK
tAC
-0.65 +0.65 -0.7
+0.7 -0.75 +0.75 -0.75 +0.75 ns
Data strobe edge to ouput data edge
tDQSQ
-
0.4
-
0.4
-
0.5
-
0.5 ns 22
Read Preamble
tRPRE 0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1 tCK
Read Postamble
tRPST 0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 tCK
CK to valid DQS-in
tDQSS 0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS-in setup time
tWPRES 0
0
0
0
ns 13
DQS-in hold time
tWPRE 0.25
0.25
0.25
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
0.2
0.2
0.2
tCK
DQS falling edge from CK rising-hold time tDSH
0.2
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH 0.35
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL 0.35
0.35
0.35
0.35
tCK
Address and Control Input setup time(fast) tIS
0.6
0.75
0.9
0.9
ns 15, 17~19
Address and Control Input hold time(fast)
tIH
0.6
0.75
0.9
0.9
ns 15, 17~19
Address and Control Input setup
tIS
0.7
0.8
1.0
1.0
ns 16~19
Address and Control Input hold time(slow) tIH
0.7
0.8
Data-out high impedence time from CK/CK tHZ
-0.65 +0.65 -0.7
Data-out low impedence time from CK/CK tLZ
-0.65 +0.65 -0.7
Mode register set cycle time
tMRD
10
12
DQ & DM setup time to DQS
tDS
0.4
0.45
DQ & DM hold time to DQS
tDH
0.4
0.45
1.0
1.0
ns 16~19
+0.7 -0.75 +0.75 -0.75 +0.75 ns 11
+0.7 -0.75 +0.75 -0.75 +0.75 ns 11
15
15
ns
0.5
0.5
ns j, k
0.5
0.5
ns _{j, k}
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
Power Down Exit Time
tIPW
2.2
2.2
2.2
2.2
ns 18
tDIPW 1.75
1.75
1.75
1.75
ns 18
tXSNR 75
75
75
75
ns
tXSRD 200
200
200
200
tCK
tREFI
7.8
7.8
7.8
7.8 us 14
tHP
tQH
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns 21
tCLmin
tHP _{or tCHmin}
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns 20, 21
tQHS
0.5
0.55
0.75
0.75 ns 21
tWPST 0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 tCK 12
tRAP
15
tDAL
tPDEX
(tWR/tCK)
+
(tRP/tCK)
1
18
(tWR/tCK)
+
(tRP/tCK)
1
20
(tWR/tCK)
+
(tRP/tCK)
1
20
(tWR/tCK)
+
(tRP/tCK)
1
tCK 23
tCK
Rev. 1.2 January 2006