S3C72Q5 Datasheet, PDF (87/330 Pages) Samsung semiconductor – 4-BIT CMOS MICROCONTROLLER

S3C72Q5/P72Q5
MEMORY MAP
IPR — Interrupt Priority Register
Bit
Identifier
RESET Value
Read/Write
Bit Addressing
3
2
1
0
IME
.2
.1
.0
0
0
0
0
W
W
W
W
1/4
4
4
4
CPU
FB2H
IME
Interrupt Master Enable Bit
0 Disable all interrupt processing
1 Enable processing for all interrupt servi ce requests
IPR.2-.0
Interrupt Priority Register Setting
IPR.2 IPR.1 IPR.0
Result of IPR Bit Setting
0
0
0 Normal interrupt handling according to default priority settings
0
0
1 Process INTB interrupt at highest priority
0
1
0 Process INT0 interrupt at highest priority
0
1
1 Process INT1 interrupt at highest priority
1
0
0 Process INTP0 interrupt at highest priority
1
0
1 Process INTT0 interrupt at highest priority
1
1
0 Process INTT1 interrupt at highest priority
1
1
1 Not available
4-21