S3C72Q5 Datasheet, PDF (261/330 Pages) Samsung semiconductor – 4-BIT CMOS MICROCONTROLLER

TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
Table 11-7. TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings
TMOD0.6
0
0
0
1
1
1
1
TMOD0.5
0
0
1
0
0
1
1
TMOD0.4
0
1
x
0
1
0
1
Resulting Counter Source and Clock Frequency
External clock input (TCL0) on rising edges
External clock input (TCL0) on falling edges
fxt (Subsytem clock: 32.768 kHz)
fxx/2¹⁰ (4.09 kHz)
fxx /2⁶ (65.5 kHz)
fxx/2⁴ (262 kHz)
fxx (4.19 MHz)
NOTE: 'fxx' = selected system clock of 4.19 MHz.
F PROGRAMMING TIP — Restarting TC0 Counting Operation
1. Set TC0 timer interval to 4.09 kHz:
BITS
SMB
LD
LD
EI
BITS
EMB
15
EA,#4CH
TMOD0,EA
IET0
2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation:
BITS
SMB
BITS
EMB
15
TMOD0.3
11-18