S3C72Q5 Datasheet, PDF (239/330 Pages) Samsung semiconductor – 4-BIT CMOS MICROCONTROLLER

I/O PORTS
PORT 0,1 CIRCUIT DIAGRAM
S3C72Q5/P72Q5
RE
P0.0/K0
P0.1/K1
P0.2/K2
P0.3/K3
P1.0/K4
P1.1/K5
P1.2/K6
RE
VDD
VDD
PM0.0
PM0.1
PM0.2
PM0.3
RE
PM0.0
PM0.0
PM0.1
PM0.2
PM0.3
PM1.0
PM1.1
PM1.2
Output
Latch
1, 4, 8
A
Internal
Latch
A
B
M
CU
DXY
S0 S1
A
B
M
Y
CU
X
D
S0 S1
MUX
AY
BS
Falling
Edge
Detection
Circuit
IRQP0
PM0.1
PM0.2
LMOD.4
LMOD.6
RE: Resistor Enable
LE: Latch Enable
LMOD.5
RE
LE
NOTES:
1. The pull-up resistor enable(RE) signal is automatically generated and synchronized to LCD segment signals.
2. When a port pin serves as an output, its pull-up resistor is automatically disabled regradless of PUMOD0.
Figure 10-1. Port 0,1 Circuit Diagram
10-6