S3C2440X Datasheet, PDF (81/429 Pages) Samsung semiconductor – 16/32-bit RISC microprocessor

NAND FLASH CONTROLLER
2003.09.25
S3C2440X RISC MICROPROCESSOR
MAIN DATA AREA ECC0 STATUS REGISTER
Register Address R/W
Description
NFMECC0 0x4E00002C R NAND Flash ECC register for data[7:0]
NFMECC1 0x4E000030 R NAND Flash ECC register for data[15:8]
Reset Value
0xXXXXXX
0xXXXXXX
NFMECC0
MECC0_3
MECC0_2
MECC0_1
MECC0_0
Bit
[31:24]
[23:16]
[15:8]
[7:0]
ECC3 for data[7:0]
ECC2 for data[7:0]
ECC1 for data[7:0]
ECC0 for data[7:0]
Description
Initial State
0xXX
0xXX
0xXX
0xXX
NFMECC1
Bit
Description
Initial State
MECC1_3
[31:24] ECC3 data[15:8]
0xXX
MECC1_2
[23:16] ECC2 data[15:8]
0xXX
MECC1_1
[15:8] ECC1 data[15:8]
0xXX
MECC1_0
[7:0] ECC0 data[15:8]
0xXX
(Note) The NAND flash controller generate NFMECC0/1 when read or write main area data while the
MainECCLock(NFCONT[5]) bit is ‘0’(Unlock).
SPARE AREA ECC STATUS REGISTER
Register Address R/W
Description
NFSECC 0x4E000034 R NAND Flash ECC register for I/O [15:0]
Reset Value
0xXXXXXX
NFSECC
Bit
Description
Initial State
SECC1_1
[31:24] Spare area ECC1 Status for I/O[15:8]
0xXX
SECC1_0
[23:16] Spare area ECC0 Status for I/O[15:8]
0xXX
SECC0_1
[15:8] Spare area ECC1 Status for I/O[7:0]
0xXX
SECC0_0
[7:0] Spare area ECC0 Status for I/O[7:0]
0xXX
(Note) The NAND flash controller generate NFSECC when read or write spare area data while the
SpareECCLock(NFCONT[6]) bit is ‘0’(Unlock).
6-20
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.