S3C2440X Datasheet, PDF (377/429 Pages) Samsung semiconductor – 16/32-bit RISC microprocessor

S3C2440X RISC MICROPROCESSOR
2003.09.25
CAMERA INTERFACE
CONTROL REGISTER
Register
CTRL
Address
R/W
0x4F0000BC
W
Description
Camera interface control
Reset Value
0x00000000
CTRL
SOFTRST
ABSAME
BENAS
CAMRST
IMGCAPA
IRQFREE
TESTPT
SWAPYUV
YUVORD
UVOFFSET
Bit
[30]
[29]
[20]
[19]
[18]
[17]
[16:14]
[13]
[12]
[11]
Description
This bit indicates software reset of camera interface.
1 = software reset
0 = normal
This bit indicates which is same both A-port image and B-port
image. If this bit is 1, A/B-port image will be the scaled images.
This bit indicates the controllability of burst length for DMA
operations.
1 = software gives burst length
0 = self burst length generation
This bit indicates the software reset of external camera processor.
1 = software reset for camera processor
0 = normal
This bit indicates the image capture enable for A-port. If this bit set
to 1, one clock pulse will be internally generated.
This bit can clear the interrupt of camera interface.
1 = Interrupt clear
0 = normal
These bits indicate the test pattern for verifying the incoming ITU-R
BT.601/656 sync signals and fundamental operations.
000 = bypass (external input)
001 = color-bar pattern
010 = square-box pattern
011 = solid-line pattern
100 = check pattern
101 = horizontal increasing pattern
110 = DC pattern
111 = reserved.
This bit controls the swap between Y and UV sequence.
1 = UYVY
0 = YUYV (recommended)
This bit indicates Y/UV order. It is recommended to fix 0.
This bit indicates the data offset of UV signals.
1 = offset binary
0 = normal (recommended)
Initial State
0
0
0
0
0
0
000
0
0
0
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
23-25