S3C2440X Datasheet, PDF (355/429 Pages) Samsung semiconductor – 16/32-bit RISC microprocessor

S3C2440X RISC MICROPROCESSOR
2003.09.25
CAMERA INTERFACE
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Figure 23-3. ITU-R BT.656 Input timing diagram
There are two timing reference signals in ITU-R BT.656 format, one at the beginning of each vedio data block
(start of active video, SAV) and one at the end of each video data block(end of active video, EAV) as shown in
Figure 23-3 and Table 23-2.
Data bit number
9 (MSB)
First word
(FF)
1
Second word
(00)
0
Third word
(00)
0
Forth word
(XY)
1
8
1
0
0
F
7
1
0
0
V
6
1
0
0
H
5
1
0
0
P3
4
1
0
0
P2
3
1
0
0
P1
2
1
0
0
P0
1 (Note 1)
1
0
0
0
0
1
0
0
0
Note 1) For compatibility with existing 8-bit interfaces, the values of bits D1 and D0 are not defined.
F = 0 (during field 1), 1 (during field 2)
V = 0 (elsewhere), 1 (during field blanking)
H = 0 (in SAV : Start of Active Video), 1 (in EAV : End of Active Video)
P0, P1, P2, P3 = protection bit
Table 23-2. Video timing reference codes of ITU-R BT.656 format
Camera interface logic can catch the video sync bits like H(SAV,EAV) and V(Frame Sync) after reserved data as
“FF-00-00”.
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
23-3