S3C2440X Datasheet, PDF (145/429 Pages) Samsung semiconductor – 16/32-bit RISC microprocessor

I/O PORTS
2003.09.25
S3C2440X RISC MICROPROCESSOR
MISCELLANEOUS control register(MISCCR)
In Sleep mode, the data bus(D[31:0] or D[15:0] can be set as Hi-Z and Output ‘0’ state. But, because of the
characteristics of IO pad, the data bus pull-up resisters have to be turned on or off to reduce the power
consumption. D[31:0] pin pull-up resisters can be controlled by MISCCR register.
Pads related USB are controlled by this register for USB host, or for USB device.
Register
MISCCR
Address
0x56000080
R/W
Description
R/W Miscellaneous control register
Reset Value
0x10330
MISCCR
Reserved
Reserved
Reserved
BATTFLT_INTR
BATTFLT_FUNC
OFFREFRESH
nEN_SCLK1
nEN_SCLK0
nRSTCON
Reserved
SEL_SUSPND1
SEL_SUSPND0
CLKSEL1
Bit
Description
[24] Reserve to 0.
[23] Reserve to 0.
[22] This bit must be 1.
[21] BATT_FLT Interrupt On/Off.
0: Enable
1: Disable
When 1, Battery fault interrupt will be masked by hardware.
[20] BATT_FLT function On/Off.
0: Enable
1: Disable
When 0, Battary fault function will be turned on.
[19] 0: Self refresh retain disable 1: Self refresh retain enable
When 1, After wake-up from sleep, The self-refresh will be
retained.
[18] SCLK0 output enable
0: SCLK1 = SCLK , 1: SCLK1 = 0
[17] SCLK0 output enable
0: SCLK0 = SCLK , 1: SCLK 0 = 0
[16] nRSTOUT' S/W reset
0: nRSTOUT = 0, 1: nRSTOUT = 1
[15:14] -
[13] USB Port 1 Suspend mode
0 = normal mode 1= suspend mode
[12] USB Port 0 Suspend mode
0 = normal mode 1= suspend mode
[10:8]
001 = Select UPLL output with CLKOUT0 pad
011 = Select HCLK with CLKOUT1 pad
100 = Select PCLK with CLKOUT1 pad
101 = Select DCLK1 with CLKOUT1 pad
11x = reserved
Reset Value
0
0
0
0
0
0
0
0
1
00
0
0
011
9-24
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.