S5N8944B Datasheet, PDF (8/21 Pages) Samsung semiconductor – G.Lite ADSL Transceiver for CO and CPE

5. Pin Description
S5N8944B
G.Lite ADSL Transceiver for CO and CPE
Table 1: Pin Description of the S5N8944B
No
Name
155 RESET_N
147 XTAL_IN
146 XTAL_OUT
67 EXT_CLK
152 PLL_FLT
158 TEST_MODE
41 TEST_SCN_EN
159 CO_RT
93 TX_SHOW
94 RX_SHOW
123 NTR
I/O
Description
I System Master Reset (Active Low)
I System Master Clock
O
(17.664MHz Xtal Oscillator for CO,
VCXO for CPE)
I
External Clock for Test
(Not Used in Normal Mode, Pull-Down)
O PLL Pump Out
I [0] Normal Mode, [1] Test Mode
I
Scan Enable
(Set to ‘0’ in Normal Mode)
I [0] CO, [1] CPE
O
Tx Showtime
(Active High. Connect to LED)
O
Rx Showtime
(Active High. Connect to LED)
I/O
ATM Network Timing Reference (8KHz)
(I: CO_RT=1, O: CO_RT=0)
108 TX_ADDR_4
109 TX_ADDR_3
110 TX_ADDR_2
111 TX_ADDR_1
112 TX_ADDR_0
113 TX_DATA_7
114 TX_DATA_6
115 TX_DATA_5
116 TX_DATA_4
119 TX_DATA_3
120 TX_DATA_2
121 TX_DATA_1
122 TX_DATA_0
105 TX_CLK
104 TX_ENB
106 TX_SOC
107 TX_CLAV
I Utopia Tx Address [4:0]
I Utopia Tx Data [7:0]
I Utopia Tx Clock (25MHz)
I Utopia Tx Enable
I Utopia Tx Start of Cell
OZ Utopia Tx Cell Available
130 RX_ADDR_4
131 RX_ADDR_3
132 RX_ADDR_2
133 RX_ADDR_1
134 RX_ADDR_0
135 RX_DATA_7
136 RX_DATA_6
137 RX_DATA_5
138 RX_DATA_4
139 RX_DATA_3
I Utopia Rx Address [4:0]
OZ Utopia Rx Data [7:0]
CONFIDENTIAL
8
Preliminary Information (Rev.2.1 )