S5N8944B Datasheet, PDF (3/21 Pages) Samsung semiconductor – G.Lite ADSL Transceiver for CO and CPE

S5N8944B
G.Lite ADSL Transceiver for CO and CPE
List of Figures
Figure 1: General Block Diagram ...................................................................................... 5
Figure 2: Logical Symbol Diagram of the S5N8944B ......................................................... 6
Figure 3: Pin Configuration of the S5N8944B .................................................................... 7
Figure 4: Functional Block Diagram of the S5N8944B ..................................................... 12
Figure 5: AFE Data I/F Timing Diagram........................................................................... 13
Figure 6: AFE Control I/F Timing Diagram....................................................................... 13
Figure 7: Motorola Read Cycle Timing Diagram .............................................................. 14
Figure 8: Motorola Write Cycle Timing Diagram .............................................................. 14
Figure 9: Intel Read Cycle Timing Diagram ..................................................................... 15
Figure 10: Intel Write Cycle Timing Diagram ................................................................... 15
Figure 11: Non-ATM I/F (Byte Mode) Timing Diagram ..................................................... 16
Figure 12: Non-ATM I/F (Envelope Mode) Timing Diagram ............................................. 16
Figure 13: ATM I/F (UTOPIA-2 Transmit) Timing Diagram............................................... 17
Figure 14: ATM I/F (UTOPIA-2 Receive) Timing Diagram................................................ 17
Figure 15: 160-QFP Package Diagram............................................................................ 20
CONFIDENTIAL
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Preliminary Information (Rev.2.1 )