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S5N8944B Datasheet, PDF (15/21 Pages) Samsung semiconductor – G.Lite ADSL Transceiver for CO and CPE
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S5N8944B
G.Lite ADSL Transceiver for CO and CPE
HS_ADDR[9:0]
HS_DATA[15:0]
HS_CS_N
HS_RD_N
HS_READY
t1
t2
t3
VALID
t6
t4
t5
Parameter
t1
t2
t3
t4
t5
t6
Description
HS_ADDR setup to HS_CS_N ↓
HS_CS_N ↓ before HS_RD_N ↓
HS_DATA valid from HS_RD_N ↓
HS_CS_N ↑ from HS_RD_N ↑
HS_READY ↓ from HS_RD_N ↓
HS_DATA hold after HS_RD_N ↑
Min Max Unit
0
ns
0
ns
170
ns
0
ns
0
20
ns
5
ns
Figure 9: Intel Read Cycle Timing Diagram
HS_ADDR[9:0]
HS_DATA[15:0]
HS_CS_N
HS_WR_N
HS_READY
t1
t2
t3
t5
VALID
t6
t4
Parameter
t1
t2
t3
t4
t5
t6
Description
HS_ADDR setup to HS_CS_N ↓
HS_CS_N ↓ before HS_WR_N ↓
HS_DATA valid from HS_WR_N ↓
HS_CS_N ↑ from HS_WR_N ↑
HS_READY ↓ from HS_WR_N ↓
HS_DATA hold after HS_WR_N ↑
Min Max Unit
0
ns
0
ns
50
ns
0
ns
0
20
ns
5
ns
Figure 10: Intel Write Cycle Timing Diagram
CONFIDENTIAL
15
Preliminary Information (Rev.2.1 )
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