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S5N8944B Datasheet, PDF (14/21 Pages) Samsung semiconductor – G.Lite ADSL Transceiver for CO and CPE
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S5N8944B
G.Lite ADSL Transceiver for CO and CPE
HS_ADDR[9:0]
HS_DATA[15:0]
t1
HS_CS_N
HS_WR_N
t2
HS_READY
(DTACKN)
VALID
t5
t3
t4
Parameter
t1
t2
t3
t4
t5
Description
HS_ADDR setup to HS_CS_N ↓
HS_WR_N ↑ before HS_CS_N ↓
HS_DATA valid from HS_READY ↓
HS_READY hi-Z from HS_CS_N ↑
HS_DATA hold after HS_CS_N ↑
Min Max Unit
0
ns
0
ns
10
ns
1
5
ns
5
ns
Figure 7: Motorola Read Cycle Timing Diagram
HS_ADDR[9:0]
HS_DATA[15:0]
t1
t3
VALID
HS_CS_N
t2
t5
HS_WR_N
t4
HS_READY
(DTACKN)
Parameter
t1
t2
t3
t4
t5
Description
HS_ADDR setup to HS_CS_N ↓
HS_WR_N ↓ before HS_CS_N ↓
HS_DATA valid from HS_CS_N ↓
HS_READY hi-Z from HS_CS_N ↑
HS_DATA hold after HS_CS_N ↑
Min Max Unit
0
ns
0
ns
50
ns
1
5
ns
5
ns
Figure 8: Motorola Write Cycle Timing Diagram
CONFIDENTIAL
14
Preliminary Information (Rev.2.1 )
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