K4F171611D Datasheet, PDF (8/34 Pages) Samsung semiconductor – 1M x 16Bit CMOS Dynamic RAM with Fast Page Mode

K4F171611D, K4F151611D
K4F171612D, K4F151612D
13. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
14. tCWL is specified from W falling edge to the earlier CAS rising edge.
15. tCSR is referenced to the earlier CAS falling edge before RAS transition low.
16. tCHR is referenced to the later CAS rising edge after RAS transition low.
CMOS DRAM
RAS
LCAS
UCAS
tCSR
tCHR
17. tDS, tDH is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)
18. If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.
19. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed
within 64ms/16ms before and after self refresh, in order to meet refresh specification.
20. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.