K4D623238B-GC Datasheet, PDF (8/17 Pages) Samsung semiconductor – 64Mbit DDR SDRAM

K4D623238B-GC
64M DDR SDRAM
MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE (The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A 0 ~ A 10 and BA0, BA1 in the same cycle as CS, RAS, CAS and W E going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,
addressing mode uses A 3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A 8 is
used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
BA1 BA0 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 Address Bus
RFU 0
RFU
DLL TM
CAS Latency
BT
Burst Length
Mode Register
DLL
A8
0
1
DLL Reset
No
Yes
Test Mode
A7
mode
0
Normal
1
Test
Burst Type
A3
Type
0 Sequential
1 Interleave
BA 0
0
1
An ~ A0
MRS
EMRS
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
CAS Latency
A6 A5 A4
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Latency
Reserved
Reserved
Reserved
3
4
5
Reserved
Reserved
Burst Length
A2 A1 A0
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
Burst Type
Sequential Interleave
Reserve
Reserve
2
2
4
4
8
8
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Full page
Reserve
MRS Cycle
CK, CK
Command
0
1
2
3
4
5
6
NOP
Precharge
All Banks
NOP
NOP
MRS
NOP
Any
Command
tRP
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
tMRD=2 tCK
7
NOP
8
NOP
-8-
Rev. 1.4 (Sep. 2002)