KAB01D100M Datasheet, PDF (68/72 Pages) Samsung semiconductor – Multi-Chip Package MEMORY

KAB0xD100M - TxGP
SEC Only
MCP MEMORY
TIMING WAVEFORM OF WRITE CYCLE(3)(UB, LB Controlled, ZZ=VIH)
Address
CS_U
UB, LB
WE
Data in
tAS(3)
tWC
tCW(2)
tAW
tBW
tWP(1)
tWR(4)
tDW
tDH
Data Valid
Data out
High-Z
High-Z
(WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS_U and low WE. A write begins when CS_U goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS_U goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS_U going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS_U or WE going high.
TIMING WAVEFORM OF DEEP POWER DOWN MODE
ZZ
Normal Operation
MODE
0.5µs
Suspend
CS_U
Read Operation Twice or Stay High during 300µs
200µs
Wake up
Normal Operation
Deep Power Down Mode
(DEEP POWER DOWN MODE)
1. When you toggle ZZ pin low, the device gets into the Deep Power Down mode after 0.5µs suspend period.
2. To return to normal operation, the device needs Wake Up period.
3. Wake Up sequence is just the same as Power up sequences.
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Revision 1.11
August 2003