KAB01D100M Datasheet, PDF (57/72 Pages) Samsung semiconductor – Multi-Chip Package MEMORY

KAB0xD100M - TxGP
NOR Flash SWITCHING WAVEFORMS
RESET Timing Diagram
R/B_R
High
CE_R or OE
SEC Only
MCP MEMORY
tRH
RESET
tRP
R/B_R
CE_R or OE
RESET
tREADY
Reset Timings NOT during Internal Routine
tREADY
tRB
tRP
Reset Timings during Internal Routine
Power-up and RESET Timing Diagram
RESET
tRSTS
Vcc
Address
DATA
Parameter
RESET Pulse Width
RESET Low to Valid Data
(During Internal Routine)
RESET Low to Valid Data
(Not during Internal Routine)
RESET High Time Before Read
R/B_R Recovery Time
RESET High to Address Valid
RESET Low Set-up Time
tAA
Symbol
tRP
tREADY
tREADY
tRH
tRB
tRSTW
tRSTS
70ns
Min
Max
500
-
-
20
-
500
50
-
0
-
200
-
500
-
80ns
Unit
Min
Max
500
-
ns
-
20
µs
-
500
ns
50
-
ns
0
-
ns
200
-
ns
500
-
ns
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Revision 1.11
August 2003