KAB01D100M Datasheet, PDF (47/72 Pages) Samsung semiconductor – Multi-Chip Package MEMORY

KAB0xD100M - TxGP
SEC Only
MCP MEMORY
NOR Flash AC CHARACTERISTICS
Write(Erase/Program)Operations
Alternate CE_R Controlled Writes
Parameter
Write Cycle Time (1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Output Enable Setup Time (1)
Output Enable
Hold Time
Read (1)
Toggle and Data Polling (1)
WE Setup Time
WE Hold Time
CE_R Pulse Width
CE_R Pulse Width High
Programming Operation
Word
Byte
Accelerated Programming Operation
Word
Byte
Block Erase Operation (2)
BYTE Switching Low to Output HIGH-Z
NOTES: 1. Not 100% tested.
2.This does not include the preprogramming time.
Symbol
tWC
tAS
tAH
tDS
tDH
tOES
tOEH1
tOEH2
tWS
tWH
tCP
tCPH
tPGM
tACCPGM
tBERS
tFLQZ
70ns
Min
Max
70
-
0
-
45
-
35
-
0
-
0
-
0
-
10
-
0
-
0
-
35
-
25
-
14(typ.)
9(typ.)
9(typ.)
7(typ.)
0.7(typ.)
25
-
80ns
Unit
Min
Max
80
-
ns
0
-
ns
45
-
ns
35
-
ns
0
-
ns
0
-
ns
0
-
ns
10
-
ns
0
-
ns
0
-
ns
35
-
ns
25
-
ns
14(typ.)
µs
9(typ.)
µs
9(typ.)
µs
7(typ.)
µs
0.7(typ.)
sec
25
-
ns
ERASE AND PROGRAM PERFORMANCE
Parameter
Block Erase Time
Chip Erase Time
Word Programming Time
Byte Programming Time
Accelerated Byte/Word
Program Time
Chip Programming Time
Erase/Program Endurance
Word Mode
Byte Mode
Word Mode
Byte Mode
Min
-
-
-
-
-
-
-
-
100,000
Limits
Typ
0.7
98
14
9
9
7
59
75
-
Unit
Max
Comments
15
sec
Excludes 00H programming
prior to erasure
-
sec
330
µs Excludes system-level overhead
210
µs Excludes system-level overhead
210
µs Excludes system-level overhead
150
µs Excludes system-level overhead
177
sec
Excludes system-level overhead
225
sec
-
cycles
Minimum 100,000 cycles guaran-
teed
NOTES: 1. 25 °C, Vcc_R = 2.9V 100,000 cycles, typical pattern.
2. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte.
In the preprogramming step of the Internal Erase Routine, all bytes are programmed to 00H before erasure.
- 47 -
Revision 1.11
August 2003