S3C2500B Datasheet, PDF (60/623 Pages) Samsung semiconductor – 32-Bit RISC Microprocessor

PRODUCT OVERVIEW
S3C2500B
Group
HDLC0
(8)
Table 1-1. S3C2500B Signal Descriptions (Continue)
Pin Name
HnCTS0/
GPIO44
HnDCD0/
GPIO45
HRXC0/DCL/
GPIO46
HTXC0/FSC/
GPIO47
Pin Type
1
I/O
1
I/O
1
I/O
1
I/O
Pad Type
phbst8
phbst8
phbst8
phbst8
Description
HDLC Ch-0 Clear To Send.
The S3C2500B stores each transition of nCTS
to ensure that its occurrence will be
acknowledged by the system.
General I/O Port.
HDLC Ch-0 Data Carrier Detected.
A high level on this pin resets and inhibits the
receiver operation. Data from a previous
frame that may remain in the RxFIFO is
retained. The pin state of transition is stored
by the register.
General I/O Port.
IOM2 Data Clock.
HDLC Ch-0 Receiver Clock.
When this clock input is used as the receiver
clock, the receiver samples the data on the
positive or negedge of HRXC0 clock. This can
be determined by S/W selection. This clock
can be the source clock of the receiver, the
baud rate generator, or the DPLL.
General I/O Port.
IOM2 Frame Syncronization Clock.
HDLC Ch-0 Transmitter Clock.
When this clock input is used as the
transmitter clock, the transmitter shifts data on
the positive or negative transition of the
HTXC0 clock input. This can be determined by
S/W selection. If you don’t use HTXC0 as the
transmitter clock, you can use it as an output
pin for monitoring internal clock such as the
transmitter clock, receiver clock, and baud
rate generator output clocks.
General I/O Port.
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