S3C2500B Datasheet, PDF (401/623 Pages) Samsung semiconductor – 32-Bit RISC Microprocessor

S3C2500B
HDLC CONTROLLER
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
0
DDD
PPT
LLx
L LN
T OO
MM
DD
TR
xx
FN
DO
DRD
Rx T
xIx
FEA
DRB
RT
RRRRRRRRRTRT T T T T
R
xxxxxxxxxxxxxxxx
x
ONCA I FSDF F FUSCF F
R
VORBDVDCDGA C TAC
B
CT L CD
TS
EED
S
[16] Rx abort (RxABT)
0= Normal operation
1 = Seven or more consecutive 1s have been received, in-frame condition.
[17] Rx CRC error (RxCRCE)
0 = Normal operation
1 = A frame Rx operation is completed with a CRC error.
[18] Rx non-octet align (RxNO)
0 = Received frame is octet.
1 = Received frame is not octet.
[19] Rx overrun (RxOV)
0 = Normal operation
1 = Received data is transferred into the RxFIFO when it is full.
[20] Reserved
[21] Reserved
[22] DMA Tx abort (DTxABT)
0 = Normal operation
1 = Abort signal is sended and DMA Tx enable bit is cleared.
[23] Rx internal error (RxIERR)
0 = Normal operation
1 = Received frame is not stable due to receive clock is unstable.
[24] DMA Rx frame done every received frame (DRxFD)
0 = Normal operation
1 = DMA Rx operation has successfully transferred a frame from RxFIFO to buffer memory.
[25] Reserved
[26] DMA Rx not owner (DRxNO)
0 = DMA has the ownership.
1 = CPU has the ownership.
[27] DMA Tx frame done (DTxFD)
0 = Normal operation
1 = DMA Tx operation has successfully transferred a frame from memory to TxFIFO.
[28] Reserved
[29] DMA Tx not owner (DTxNO)
0 = DMA has the ownership.
1 = CPU has the ownership.
[30] DPLL one clock missing (DPLLOM)
0 = Normal operation
1 = Set in FM/Machester mode when DPLL does not detect an edge on the first entry.
[31] DPLL two clock missing (DPLLTM)
0 = Normal operation
1 = DPLL was not detected on two consecutive edges an search mode sas entered.
Figure 8-15. HDLC Status Register (Continued)
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