S3C2500B Datasheet, PDF (508/623 Pages) Samsung semiconductor – 32-Bit RISC Microprocessor

S3C2500B
GDMA CONTROLLER
12 GDMA CONTROLLER
12.1 OVERVIEW
The S3C2500B has a six-channel General DMA controller, called the GDMA. The six-channel GDMA performs
the following data transfers without CPU intervention:
• Memory-to-Memory (Memory to/from Memory, Memory to/from USB)
• External Device-to-Memory (External Device to/from Memory)
• HUART0/1-to-Memory (High-speed UART serial port0/1 to/from Memory)
• DES-to-Memory (DES to/from Memory)
The on-chip GDMA can be started by software and/or an external GDMA request (xGDMA_Req), HUART0
request, HUART1 request, or DES request. Software can also be used to restart a GDMA operation after it has
been stopped.
The CPU can recognize when a GDMA operation has been completed by software polling and/or when it receives
an appropriate internally generated GDMA interrupt. The S3C2500B GDMA controller can increment or
decrement source destination addresses and conduct 8-bit (byte), 16-bit (half-word) or 32-bit (word) data transfer.
The GDMA does not check the cache coherency. So software must ensure that source and destination addresses
must be configured as non-cacheable in the memory system configuration when it configures the GDMA
channels.
The local priority of six-channel GDMA can be programmed by fixed priority or round-robin priority in similar
manner to the AHB bus priority. Please refer to Chapter 4, The System Configuration.
12.2 FEATURE
• Six GDMA Channels
• Memory to Memory Data Transfer
• Memory to Peripheral Data Transfer (High Speed UART, DES, USB)
• Support for Four External GDMA Request from GDMA Request Pins (xGDMA_Req0 – xGDMA_Req3)
12-1