S3C2500B Datasheet, PDF (307/623 Pages) Samsung semiconductor – 32-Bit RISC Microprocessor

S3C2500B
I²C CONTROLLER
6.5.2 SHIFT BUFFER REGISTER (IICBUF)
The shift buffer register for the I²C described in Table 6-4.
Register
IICBUF
Address
0xF00F0004
Table 6-3. IICBUF Register
R/W
R/W
Description
Shift buffer register
Rest Value
Undefined
Bit Number
Bit Name
[7:0]
Data
[31:8]
Reserved
Table 6-4. IICBUF Register Description
Description
This data field acts as serial shift register and read buffer for interfacing to
the I²C. All read and write operations to/from the I²C are done via this
register. The IICBUF register is a combination of a shift register and a data
buffer. 8-bit parallel data is always written to the shift register, and read form
the data buffer. I²C data is always shifted in or out of the shift register.
Not applicable.
6.5.3 PRESCALER REGISTER (IICPS)
The prescaler register for the I²C is described in Table 6-6.
Register
IICPS
Address
0xF00F0008
Table 6-5. IICPS Register
R/W
R/W
Description
Prescaler register
Rest Value
0x00000000
Bit Number
[15:0]
[31:16]
Bit Name
Prescaler value
Reserved
Table 6-6. IICPS Register Description
Description
This prescaler value is used to generate the serial I²C clock. The system
clock is divided by (16 x (prescaler value + 1) + 3) to make the serial I²C
clock. If the prescaler value is zero, the system clock is when divided by 19
to make the serial I²C clock. Therefore, when I²C is used to 100kbit/s in the
standard mode, the prescaler value must be changed.
Not applicable.
6-11