K4S640432H-UC Datasheet, PDF (6/14 Pages) Samsung semiconductor – 64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant)

SDRAM 64Mb H-die (x4, x8, x16)
CMOS SDRAM
PIN CONFIGURATION (Top view)
x16 x8 x4
VDD
VDD
VDD
1
DQ0 DQ0 N.C
2
VDDQ VDDQ VDDQ
3
DQ1 N.C N.C
4
DQ2 DQ1 DQ0
5
VSSQ VSSQ VSSQ
6
DQ3 N.C N.C
7
DQ4 DQ2 N.C
8
VDDQ VDDQ VDDQ
9
DQ5 N.C N.C
10
DQ6 DQ3 DQ1
11
VSSQ VSSQ VSSQ
12
DQ7 N.C N.C
13
VDD
VDD
VDD
14
LDQM N.C N.C
15
WE WE WE
16
CAS CAS CAS
17
RAS RAS RAS
18
CS
CS
CS
19
BA0 BA0 BA0
20
BA1 BA1 BA1
21
A10/AP A10/AP A10/AP
22
A0
A0
A0
23
A1
A1
A1
24
A2
A2
A2
25
A3
A3
A3
26
VDD
VDD
VDD
27
x4 x8 x16
54
VSS
VSS
VSS
53 N.C
DQ7
DQ15
52
VSSQ
VSSQ
VSSQ
51 N.C
N.C
DQ14
50 DQ3
DQ6
DQ13
49
VDDQ
VDDQ
VDDQ
48 N.C
N.C
DQ12
47 N.C
DQ5
DQ11
46
VSSQ
VSSQ
VSSQ
45 N.C
N.C
DQ10
44 DQ2
DQ4
DQ9
43
VDDQ
VDDQ
VDDQ
42 N.C
N.C
DQ8
41
VSS
VSS
VSS
40 N.C/RFU N.C/RFU N.C/RFU
39 DQM DQM UDQM
38 CLK
CLK
CLK
37 CKE
CKE
CKE
36 N.C
N.C
N.C
35 A11
A11
A11
34 A9
A9
A9
33 A8
A8
A8
32 A7
A7
A7
31 A6
A6
A6
30 A5
A5
A5
54Pin TSOP (II)
29 A4
A4
A4
(400mil x 875mil)
28
VSS
VSS
VSS
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System clock
CS
Chip select
CKE
Clock enable
A0 ~ A11
Address
BA0 ~ BA1 Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM
DQ0 ~ X15
VDD/VSS
VDDQ/VSSQ
N.C/RFU
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No connection
/reserved for future use
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11,
Column address : (x4 : CA0 ~ CA9, x8 : CA0 ~ CA8 , x16 : CA0 ~ CA7)
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
Rev. 1.3 August 2004