K4S640432H-UC Datasheet, PDF (3/14 Pages) Samsung semiconductor – 64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant)

SDRAM 64Mb H-die (x4, x8, x16)
CMOS SDRAM
4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
• Pb-free Package
• RoHS compliant
GENERAL DESCRIPTION
The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x
4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No.
K4S640432H-UC(L)75
K4S640832H-UC(L)75
K4S641632H-UC(L)60
K4S641632H-UC(L)70
K4S641632H-UC(L)75
Orgainization
16Mb x 4
8Mb x 8
4Mb x 16
Max Freq.
133MHz(CL=3)
133MHz(CL=3)
166MHz(CL=3)
143MHz(CL=3)
133MHz(CL=3)
Interface
LVTTL
Package
54pin TSOP(II)
Organization
16Mx4
8Mx8
4Mx16
Row Address
A0~A11
A0~A11
A0~A11
Column Address
A0-A9
A0-A8
A0-A7
Row & Column address configuration
Rev. 1.3 August 2004