K4S281632O-LC75000 Datasheet, PDF (4/18 Pages) Samsung semiconductor – 54TSOP(II) with Lead-Free & Halogen-Free (RoHS compliant)

K4S280832O
K4S281632O
datasheet
1. KEY FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
• 54pin TSOP II Lead-Free and Halogen-Free package
• RoHS compliant
Rev. 1.0
SDRAM
2. GENERAL DESCRIPTION
The K4S280832O / K4S281632O is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits / 4 x
2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
3. ORDERING INFORMATION
Part No.
K4S280832O-LC/L75
K4S280832O-LC/L60
K4S281632O-LC/L75
K4S281632O-LC/L60
Orgainization
16Mb x 8
16Mb x 8
8Mb x 16
8Mb x 16
Max Freq.
133MHz (CL=3)
166MHz (CL=3)
133MHz (CL=3)
166MHz (CL=3)
[ Table 1 ] Row & Column address configuration
Organization
16Mx8
8Mx16
Row Address
A0~A11
A0~A11
Column Address
A0-A9
A0-A8
Interface
LVTTL
Package
54pin TSOP(II)
Lead-Free & Halogen-Free
-4-