K4H510738E Datasheet, PDF (4/22 Pages) Samsung semiconductor – Stacked 512Mb E-die DDR SDRAM Specification (x4/x8)

DDR SDRAM stacked 512Mb E-die (x4/x8)
Pin Description
DDR SDRAM
st.64Mb x 8
st.128Mb x 4
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
WE
CAS
RAS
CS0
CS1
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
WE
CAS
RAS
CS0
CS1
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1
66
2
65
3
64
4
63
5
62
6
61
7
60
8
59
9
58
10
66Pin TSOPII
57
11 _{(400mil x 875mil)} 56
12 _{(0.65mm Pin Pitch)} 55
13
54
14
Bank Address
15
BA0~BA1
53
52
16
51
17
50
18
Auto Precharge ₄₉
A10
19
48
20
47
21
46
22
45
23
44
24
43
25
42
26
41
27
40
28
39
29
38
30
37
31
36
32
35
33
34
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE0
CKE1
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE0
CKE1
A12
A11
A9
A8
A7
A6
A5
A4
VSS
stacked 512Mb TSOP-II Package Pinout
Organization
st.128Mx4
st.64Mx8
Row Address
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.0 July. 2003