K4H510738E Datasheet, PDF (3/22 Pages) Samsung semiconductor – Stacked 512Mb E-die DDR SDRAM Specification (x4/x8)

DDR SDRAM stacked 512Mb E-die (x4/x8)
DDR SDRAM
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe DQS
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
Ordering Information
Part No.
K4H510638E-TC/LAA
K4H510638E-TC/LA2
K4H510638E-TC/LB0
K4H510738E-TC/LAA
K4H510738E-TC/LA2
K4H510738E-TC/LB0
Org.
st.128M x 4
st.64M x 8
Max Freq.
AA(DDR266@CL=2)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
AA(DDR266@CL=2)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Interface
SSTL2
SSTL2
Package
66pin TSOP II
66pin TSOP II
Operating Frequencies
Speed @CL2
Speed @CL2.5
CL-tRCD-tRP
*CL : CAS Latency
AA(DDR266@CL=2.0)
133MHz
133MHz
2-2-2
A2(DDR266@CL=2.0)
133MHz
133MHz
2-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
2.5-3-3
Rev. 1.0 July. 2003