K4D261638E Datasheet, PDF (4/16 Pages) Samsung semiconductor – 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM

K4D261638E
PIN CONFIGURATION (Top View)
128M DDR SDRAM
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1
66
2
65
3
64
4
63
5
62
6
61
7
60
8
59
9
58
10 _{66 PIN TSOP(II)} 57
11 _{(400mil x 875mil)} 56
12 _{(0.65 mm Pin Pitch)} 55
13
54
14
53
15
52
16
51
17
50
18
49
19
48
20
47
21
46
22
45
23
44
24
43
25
42
26
41
27
40
28
39
29
38
30
37
31
36
32
35
33
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTION
CK,CK
CKE
CS
RAS
CAS
WE
L(U)DQS
L(U)DM
RFU
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
BA0, BA1
A0 ~A11
DQ0 ~ DQ15
VDD
VSS
VDDQ
VSSQ
NC
-4-
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ’s
Ground for DQ’s
No Connection
Rev. 1.2 (Jul. 2003)