S5L1462B Datasheet, PDF (37/43 Pages) Samsung semiconductor – CD and DVD playback

RF SIGNAL PROCESSOR
MIRROR CIRCUIT
S5L1462B
MIRRI
VCC
CB1
BOTTOM
PEAK
CP1
GND
RFRP_FRQ
-
GCA
LPF
+
GAIN_RFRP
RFRP_OFST
RFRP
RFCT
PEAK
CP2
+
COMP
-
GND
MIRR
• The RFRP circuit is a block that detects signals crossing the TRACK.
• The circuit receives AC-COUPLED RFAGCO signals and calculates the difference between two signals through
the PEAK HOLD and BOTTOM HOLD. The response time constant of the PEAK HOLD and BOTTOM HOLD is
set by Add 0CH's RFRP_FRQ, and the standard CAPACITOR value is set by the CP1 block and CAPACITOR
connected to the CB1 block. (Standard value: 100pF)
• The AMP that produces the RFRP signal by calculating the PEAK HOLD output and the BOTTOM HOLD output
receives the RFRP_OFST, and corrects the difference in DC value in the PEAK HOLD output and BOTTOM
HOLD output to guarantee a DYNAMIC RANGE and adjust the gain by GAIN_RFRP from 0dB-12dB.
• The RFRP signal is output through the R, C 1st LPF, and the LPF's BW is decided by Address 0CH's
RFRP_FRQ value.
• The CENTER voltage of the two signals that passed through the PEAK HOLD and BOTTOM HOLD is output to
the RFCT block. The response time constant of the PEAK HOLD and BOTTOM HOLD is decided by the
CAPACITOR value and resistance connected to CP2 and CB2.
• The MIRR signal is found by comparing the RFCT and RFRP signal, and the polarity is HIGH in the MIRROR
while LOW in the PIT. Also, the amount of HYSTERISIS can be adjusted by inserting resistance between the
RFCT and MIRR.
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