S5L1462B Datasheet, PDF (2/43 Pages) Samsung semiconductor – CD and DVD playback

S5L1462B
BLOCK DIAGRAM
RF SIGNAL PROCESSOR
RFSUM
ADVD
BDVD
DDVD
RREFBF
RREFEQ
RREF
VREFEQ
ADVD1
BDVD1
CDVD1
DDVD1
AVCC
VREFA
E
F
VBGRO
LD0DVD
PDDVD
LD0CD
PDCD
AGND
FE
to RF EQ
AGC_DET
tuning block
PD_POL RFSUM_SEL
MUX6
64
RF
AGCI
RFRP
63
Equalizer
62
1
2
3
4
6
7 VREF
8
EQ_FREQ.
61
RF
MUX
RFSUM $
AGC AMP
EQ_BOOST
RFCT &
SW_CON
GAIN_RFUM _{SW_CON1}
AGC_HOLD _Cpeak
PLLCTL _{PD_LIMIT}
MIRR
TBAL _DPDMUTE TE10FST
GAIN_TE1 _{AGC_LVL DPDEQ1}
VCPS
Phase
detector
LPS
S/IF
Block
60
59
58
57
56
55
TE1 ^GCA
EQ
Front
MUX
GCA
EQ
COM
COM
PDLIMITRES
Defective
waveform
FAULT
OUT
detection circuit
54
DPD
VC AMP
53
52
EQ VC
9
AMP
10
A+C
11
12
B+D
13
GAIN_ABCD
ABCDOFST
+
-^GCA
DPDEQ2
14
15
ANALOG
GAIN_FE
FEOFST
-
+
VC AMP
PLLCTL
51
FLT_CTL
HOLD_CTL
50
to DPD
Block
49
48
47
VREFA1
-
46
+ VREFAOF
45
VREFA
Interruption
44
VREFA
Detect
MUX
43
16
+
TE38
17
GAIN_FE
FEOFST
18
19
-
GAIN_TE3
TFOFST
TE_
TE MUX ^SEL
LPF
20
ALPC
LPF
INTER_TH
INT_ONB
FOK_TH DFCTTH1
DFCTTH2
21
10dB
22
10dB
42
ENVELOPE FOK DEFECT
23
ALPC_SEL
INTER
ANALOG
41
24
Detect
VC1 AMP
CP1
CB1
RFRP
CP2
Cpeak
RFCT
RESET
STB
CLOCK
DATA
PDLIMITERS
VREFDPD
DPDGND
TE1RES
PLLCTL
FAULTOUT
DPDEQ2
DPDEQ1
MIRR
DPDVCC
INTER0
INTER1
PLLDFT
DFCT1
INTER_ONB
2